Resumen
Specifies the logical layer for a set of signal lines that constitute a multiple segment bus architecture, and for the interfacing of modules connected to a bus segment. Intended to be used as a component within a profile to build systems with higher levels of compatibility.
Informaciones generales
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Estado: RetiradaFecha de publicación: 1994-12Etapa: Retirada de la Norma Internacional [95.99]
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Edición: 1Número de páginas: 208
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Comité Técnico :ISO/IEC JTC 1ICS :35.160
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